NNC-CPU-Z80 IEEE Preliminary Notes: Switch 1, Timer intervals & CPU clock. Switch on = top side depressed. Switch sections 1 to 6 timer interval Use one switch only! Sw 1-1 = 32us to 2 sec. 1-2 = 16us to 1 sec. 1-3 = 8 us to 500 ms 1-4 = 4 us to 250 ms 1-5 = 2 us to 125 ms 1-6 = 1 us to 62 ms Switch sections 7 & 8 for 2 or 4 Mhz. CPU clock. Use one switch only! Sw 1-7 = 2 Mhz. 1-8 = 4 Mhz. Serial Ports: CRT = 9600 Baud RTS & DTR active LPT = 1200 Baud RTS & DTR active Port Addrs. CRT Data = 08H Status & Control = 09H LPT Data = 0AH Status & Control = 0BH 8253 Timer ports: Timer 0 = 00H ;CRT Baud clock Timer 1 = 01H ;LPT Baud clock Timer 2 = 02H ;RTC Real time clock Control reg. = 03H 8255 Parallel ports: Port A = 04H Port B = 05H Port C = 06H Control reg. = 07H Interrupt Control Port 0EH or 0FH Extended Address Port 0CH or 0DH NNC-CPU-Z80-IEEE Page 2 Jumper Usage jumpers a,b,c,d,e,aa, and bb - parallel port jumper aa - port A - 1-2 = data out 2-4 = data in 2-3 = bidirectional data jumper bb - port B 1-2 = data out 2-3 = data in jumpers a,b,c,d,e - port C 8 = pc7 7 = pc6 6 = pc5 5 = pc4 4 = pc2 3 = pc1 a-d & b-c = data out a-b & c-d = data in 2 = pc3 1 = pc0 b-c & d-e = data out b-e & c-d = data in a-c & d-e = interrupt jumpers f & g - onboard ROM/RAM addressing f1 - g1 = A10 = two 1kbyte chip f2 - g2 = A11 = two 2kbyte chips f3 - g3 = A12 = two 4kbyte chips f4 - g4 = gnd = one chip (1,2, or 4 kbyte) jumpers h & j - onboard ROM/RAM addressing h2-j2, h3-j3, h5-j5 = e000 thru ffff h2-j2, h3-j3, h6-j6 = f000 thru ffff h2-j2, h4-j4, h6-j6 = f800 thru ffff h1-j1, h4-j4, h6-j6 = fc00 thru ffff jumpers k & l - onboard ROM/RAM power k1 = l3 = -5v k3 = l1 = +12v l7 = pin 18 of u5 l6 = pin 19 of u5 l5 = pin 21 of u5 k4 = pin 18 of u13 k2 = pin 19 of u13 l2 = pin 21 of u13 k5 = wr signal for RAM k6 = A11 k7 = A10 NNC-CPU-Z80-IEEE Page 3 jumpers n & p are covered by the blue frequency switch jumper s connects INTA to the PDBIN signal. It should be open when using the onboard 8214 interrupt controller. The jumper should be installed to use an interrupt controller somewhere else on the bus. jumper t is "wait on M1". If it is installed an automatic wait state is inserted in M1 cycles and also in interrupt acknowledge cycles. jumpers u & v connect interrupts to the vectored interrupts. 1 = 8253 timer to VI0 2 = U11 txready to VI1 3 = U11 rxready to VI2 4 = U12 txready to VI3 5 = u12 rxready to VI4 6 = U15 pc0 to VI5 7 = U15 pc3 to VI6 jumpers x & y connect signals to the Z80A NMI pin17 1 = NMI - IEEE pin 12 2 = PWRFAIL - IEEE pin 13 3 = ERROR - IEEE pin 98 jumpers z connect power on clear. 1 = onboard power on clear generator 3 = IEEE bus POC = pin 99 2 = internal reset + IEEE pin 75(preset) + IEEE pin 54(slave clr) jumpers dd & ee numbers 1 thru 8 connect CRT serial port to 50 pin conn. connecting dd2-ee2 & dd3-ee3 makes the UART a DATA TERMINAL EQUIPMENT. connecting dd4-ee4 permanently activates CTS on the UART. connecting cc4-ee4 connects UART CTS to the connector. jumpers dd & ee numbers 13 thru 20 connect LPT serial port to 50 pin conn. connecting dd14-ee14 & dd15-ee15 makes the UART a DATA COMMUNICATION EQUIPT. connecting dd14-ee15 & dd15-ee14 makes it a DATA TERMINAL equip. connecting dd17-ee17 permanently activates cts on UART U12. NNC-CPU-Z80-IEEE Page 4 Serial port strapping: CRT port; DD2-EE2, DD3-EE3, DD4-EE4 LPT port; DD14-EE15, DD15-EE14, DD17-EE17, CC17-EE16, EE18-DD20, DD18-DD19-EE20 Note: The above strappings set CTS to internal control for CRT port and LPT port. Serial port baud rates: Baud rates are programmable, and are 9600 baud for CRT, 1200 baud for LPT. To change baud rate, write a small CP/M com file or code must be added to CP/M BIOS. Example: CRT Port = 9600 Baud: ORG 100H ; MVI A,36H ;BAUD 9600 to timer 0 OUT 3 MVI A,12 OUT 0 MVI A,0 OUT 0 JMP 0 END Example: LPT Port = 1200 Baud: ORG 100H MVI A,76H ;BAUD 1200 to timer 1 OUT 3 MVI A,96 OUT 1 MVI A,0 OUT 1 JMP 0 END Example: LPT Port = 300 Baud ORG 100H MVI A,76H ;BAUD 300 to timer 1 OUT 3 MVI A,128 OUT 1 MVI A,1 OUT 1 JMP 0 END NNC-CPU-Z80-IEEE Page 5 ROM MONITOR: BC- Boot from floppy D - Display memory in HEX F - Fill memory with HEX constant G - Go to and execute H - HEX math calculator J - Justify memory M - Move memory block to other block address Q - Query I/O ports: Iaa I = Input, aa = addrs., byte read will then display Oaa,bb O = Output, aa = addrs., bb = byte to send S - Substitute memory byte in HEX V - Verify memory block with other block X - Examine and modify CPU registers Z - Memory size test NNC-CPU-Z80-IEEE Page 6 U35 IS THE Z80A cpu. IORQ is the only output requiring buffering. It has a total of 6 lpttl loads. NMI pin 17 is provided with jumpers (x &y) to permit connection to IEEE signals NMI(12), PWRFAIL(13), or ERROR(98). RDY pin 24 is supplied from IEEE signals PRDY(72) and XRDY(3), and in addition can introduce an automatic wait state on M1 cycles if the "T" jumper is installed. The eight status signals required by the IEEE bus spec are developed in a straightfoward manner with the exception of "SWO". SWO is generated by the assertion of either "IORQ" or "MREQ" in the absence of "RD", "RFSH", and "INTA". This is necessary since the Z80A does not produce "WR" until late in the write cycle. This would cause no problem if the IEEE bus spec provided for a memory request signal. Since it does not, the only status signal which can be put on the bus during a memory write cycle is "SWO". "MWRT" is generated from IEEE bus signals but is provided with a jumper( W ) per IEEE bus specs to delete it in case it is already provided elsewhere on the bus. "SXTRQ" is maintained at a logic one or inactive state. U46, an LS373 transparent latch is provided to delay slightly the termination of the Status signals to meet IEEE bus specs. U42 and U43, also LS373, similiarly delay the removal of the address signals A0-A15. "pSYNC" is developed in two different ways. During a FETCH, MEMORY READ, MEMORY WRITE, or INTERRUPT cycle, "MREQ" or "INTA" (in the absense of "RFSH") clocks U30 pin 3 (LS74 flip-flop) which in turn directly sets U30 pin 10 generatmng "pSYNC". Duriog an I/O REAT or I/O WRITE cycle, "IORQ" clocks U22 which allows the "pSYNC" flip-flop U30 to set on the next positive transition of the IEEE bus PHASE signal. In either event, "pSYNC" is clocked off on the next positive transition of the bus phase signal. "pSTVAL" is derived by delaying "pSYNC" a small amount, enough to guarantee the validity of the STATUS signals. "pSTVAL" also sets U22 pin 4 which controls the timing of "pWR" and "pDBIN". U22 is clocked off by the trailing edge of "MREQ" or "IORQ". "pDBIN" is generated by "RD" or by "INTA". "INTA", however, is provided with a jumper ( S ) to be removed if the interrupt controller is on this CPU board. In this case, the interrupt vector is not supplied externally but from within this board and "pDBIN" is not appropriate. The DATA bus drivers are U36 and U44, LS244 drivers. The output function can be disabled by "DODSB" IEEE pin 23. The input direction is controlled by "pDBIN" in the absense of onboard I/O or MEMORY access. NNC-CPU-Z80-IEEE Page 7 Two 24 pin sockets U5 and U13 are provided for onboard memory. These may be independentny either RAM or ROM, and of 8k, 16k, or 32k in size. Provision is made for software control such that they are located at all addresses (including 0) upon RESET for use during BOOT. Also under software control of U26, an LS175 latch, U5 and U13 may be returned to normal addressing and U5 and/or U13 may be removed from the address range entirely. This might be done to permit a full 64k of RAM. U18 is an 8214 interrupt controller, providing 8 levels of vectored interrupt. These may come from tle IEEE bus or from`such onboard functions as the 8253 timer, or Rxready or Txready from either 8251A UART, or from the 8255 parallel port. U24, U25, and U32 provide the I/O Port decoding. Ports 0 thru 3 activate the 8253 timer and baud rate generator. Ports 4 thru 7 activate the 8255 parallel port. Ports 8 and 9 activate the CRT serial UART. Ports A and B activate the Line Printer serial port. Ports C or D load the Extended Addressing latch U19. Ports E or F load the 8214 Interrupt controlner U18 and the onboard memory control latch U26. U15 is an 8255A parallel port. Output drivers are provided since the output current capability of the 8255A is limited. Port A driver can be jumpered to be INPUT, OUTPUT, or BIDIRECTIONAL under control of PC6 (jumper AA). Port B can be INPUT or OUTPUT (jumper BB). Port C can be used in many ways and each of the 8 data lines can be individually jumpered to be INPUT or OUTPUT (jumpers A,B,C,D,and E). Also PC0 and PC3 can become Interrupts. U11 is an 8251A UART serial port intended for the CRT system terminal, and U12 is an 8251A intended for line printer or other utility use. With the jumpers provided (CC,DD,EE) they may be independently connected as an RS232 DATA TERMINAL EQUIPMENT, or DATA COMMUNICATION EQUIPMENT. A resistor is provided at jumper DD4 and DD17 to allow permanent activation of CTS on the 8251A's if desired. Y1 is a 1.8432 mHz crystal feeding the 8253 timer U14 to supply baud rates of any value up to 19,200 to the serial ports. Under software control, each serial port may be independently set. Y2 is a 8 mHz crystal supplying either a 2 mHz or 4 mHz clock to the Z80A and thru U20 an LS393 counter selectable frequencies to the third section of the 8253 timer. Periods of 1 usec thru 32 usecs are available and with the 16 bit counter in U14 8253, real-time clock periods of slightly over 2 seconds are possible.  ar