Last updated Aug 18 2010. Edited by Herb Johnson, (c) Herb Johnson, except for content written by Lee Hart and others. Contact Herb at www.retrotechnology.com, an email address is on that page..
Lee Hart discusses an August 2010 revision of his Rev A Membership Card design. Check the Membership Card Web page for the current status of the kit. The kit at this point is in "Rev B", this page will not be updated. - Herb Johnson
Aug 6 2010 changes: The Membership board rev.A works, but there are a couple details I wanted to fix in the rev.B version. First, power consumption was higher than I'd like. This is due to the memory chip being active for the entire 8 clock cycles of an 1802 bus cycle. Second, the 74HC373 output latch was missing data on output instructions.
[The history of the 74HC373 and 4013 problem was found in the Rev A kit by Lee and Decker. See this Web page on Todd P. Decker's build and debug of the Rev A kit. - Herb]
I did some breadboarding to sort out the memory chip select and output latch timing. Here's the new schematic in ASCII (view with a fixed width font):
____ U7 74HC374
_____ OUT57 | | output latch
N+LOAD __________|D Q|_______|clk |
U4B pin 4 | | | |____| VCC
__|clk | _|_ U7 |
| |__R__| ___ C6 > R5 pin 2
1802 /MRD____ | ____| | 82pF > 100k memory /CE
U1 pin 7 | U5A | |_______U2 pin 20
| 4013 gnd _| D
1802 TPB______|______________________|| Q1 2N7000
U1 pin 33 S ||_ N-channel MOSFET
| S
A15 ____________________________________|
U3 pin 15
The changes are:
- Add Q1 to minimize memory chip active time (reduces power consumption)
- Change U7 from 74HC373 to 74HC374 (latches on rising edge of clock)
- Add C6 on U5A output (needed for slow memories or high 1802 clocks)
To minimize power consumption, the memory chip is only selected for 1 out of the 8 bus clock cycles. When A15 is low (address in the lower 0-32k of the memory map), the source of Q1 is low. Then, when TPB goes high, it turns Q1 on, pulling memory /CE low. When TPB returns low, Q1 turns off, and the 100k resistor pulls /CE back high.
To latch data in U7 during an output instruction, we need a rising edge on OUT57 while the memory is active. Since the rising edge of TPB enables memory, we need to wait for the memory chip's access time before generating the OUT57 rising edge. Memory chips range from under 100ns for new parts to 450ns or more for old chips. The 4013 provides some of the delay needed; its clock-to-Q delay is 70-300ns depending on the part. So C6 is added, to provide additional delay. It works with the output resistance of the 4013 (1k-2k) to form an RC network.
Here is the timing as it actually comes out of the 1802:
. 5 . 6 . 7 .
clock ---_________---------_________---------_________---------______
1. 300ns-->| | 300ns-->| |
TPB ____________________________________------------------___________
2. 40ns-->|| 600ns-->| |
output of MOSFET inverter ----------------_______________________----
3. Taccess 200ns-->| | Toff 50ns-->||
data from memory to 1802 --------------------<=====valid data=====>--
4. Tsetup 0ns min-->| | |<--30ns Thold
1802 latches data from memory ___---
Memory read: The 1802 starts TPB at the rising edge of clock 6, and latches data from memory at the rising edge of clock 7. The clock speed therefore determines the memory chip's access time requirements.
1/Fclock = 1 + 2 + 3 + 4
With the Membership board'5 500khz clock:
1/500khz = 2000us = 300ns + 40ns + Taccess + 0ns
Taccess = 1640ns or better
Even with a very slow chip, and running it at very low supply voltages, it should work fine.
Conversely, how fast a clock can we use with a 150ns memory chip?
1/Fclock = 300ns + 40ns + 150ns + 0ns
Fclock = 2.04 MHz
This should be plenty for the sorts of things this board will be used for. It would support an 1861, for example.
Output port: C6 isn't needed with fast memory chips, but the slower the memory, the bigger the value of C6. 68pf was enough for any of the RAMs and 4013's I had, so I selected 82pf (a value I happened to have a bunch of). I may make it bigger later, for old CMOS EPROMs. The only risk for making it too large is that it restricts the upper clock speed.
CMOS memory chip speed is directly proportional to power supply voltage. The Membership board is built for low power, like batteries or other low-voltage supplies. The output resistance of the CMOS chips like the 4013 change inversely with supply voltage (lower voltage = higher resistance). Using it as the R for C6 makes the delay increase automatically as power supply voltage is lowered.
- Lee Hart, Aug 6 2010
Update: Aug 18 2010 In addition, Lee Hart has design changes as follows:
- use 0.040" holes for all the ICs, so in-board socket pins will fit, instead of sockets - changed I/O port from 5 to 4 (same as original Elf) - added a hole for each switch, so a standard switch should fit as well as the ones I have with a wider-spaced pin - added jumper option for 1804/5/6 CPU (but no load mode). - misc. "twiddling" to increase spacing on solder-side pads to reduce chances of solder shorts
Discussion of Rev A to Rev B changes is currently in this text file.
Refer to the Membership Card home page for the current status of the Rev B kit. - Herb Johnson
This page and edited content is copyright Herb Johnson (c) 2010. Contents written by Lee Hart, are copyright Lee Hart (c) 2010. Copyright of other contents beyond brief quotes, is held by those authors. Contact Herb at www.retrotechnology.com, an email address is available on that page..