Sept 9 2024

Action of the little board under the ELF II board.

1) actions on /MREAD
--------------------

/MREAD from the processor (pin 7) went to the elfII bus (pin 30).
The mod board cuts the /MREAD line and inserts two CMOS gate delays.
The controling gate for /MREAD is enabled by a 4027 flip flop output. 

The flip flop input J is high by gate 4093 pin 4. 
The NAND gate is high by either:
- toggle switch near bus 1 connector is closed OR
- 1802 A7 and A6 are high (could be address C000H-FFFFH?)

The flip-flop is also set by the LOAD switch (toggled low). 

The flip-flops are clocked by TPA (1802 pin 34) 
- probably selects high-order address cycle? 

The flip-flops are probably reset by a push-button on a 4093 gate.


Hypothesis: /MREAD to the Elf II bus is disabled during addressing between
C000H-FFFFH. That activity depends on the position of the small toggle
switch near bus connector J1.

-------------------------------------------------------------------

2) RUN activity

A push button on a 4093 gate, also forces a low on RUN, 
through gate 4001 to 1802 RUN pin 3.
RUN is driven through an inverter A11 (4050)