Intel MCS 4/40 ROM disassembly, Dwight Elvey

Look at the Web page "intel440_roms.html" for the backround, on Dwight Elvey's examination of some Intel 4/40 PROMS. - Herb Johnson, March 22 2016.

[Events] lead me to look at the listing you have for your Intellec 4/40. I started by looking at the TTY/serial section. It seems that who ever did the changes to your code wanted to do 1200 baud ( look at the calculations I did below ). He'd given up one of the commands to have two different delays one for serial and one for programming. Clearly not an Intel hack, as he didn't patch the command table.

I doubt it was a factory suggested change. I'd guess it was an attempt to make it work a little faster. Here are my calculations: ( see below)

Then I redid some of the calculations for baud rates. Kyle's comes out to 108.8 or 108.9 depending on input or output. That is close enough to 110 baud to not be an issue. Yours come out to 1382 and 1402.I suspect the fellow was trying to hit 1200 baud but didn't account for all the cycles in handling the data. - Dwight

[My first calculations:}

Kyle's serial
-------------

delayCount equ 03ch
  DelayBaudRate:
0359 20 3C  fim r0r1,delayCount  ;  2 cycles

  DBRLoop1: 
035b 71 5B  isz r1,DBRLoop1  ; 16-12=4 fisrt pass 16 on loops
035d 70 5B  isz r0,DBRLoop1  ; 0Fh-3=0Ch +1 for last incr

4 + 12*(16+1) +1 = 209 loops or 418 cycles

  DelayBaudRateHalf:
035f 20 3C  fim r0r1,delayCount  ; as above. 2 cycles

  DBRLoop2: 
0361 71 61  isz r1,DBRLoop2 
0363 70 61  isz r0,DBRLoop2

418 cycles as above

0365 C0   bbl 0	;1 cycle

14 cycles TX overhead
2 + 418 + 2 + 418 + 1 + 14 = 855 instruction cycles

15 cycles RX overhead
2 + 418 + 2 + 418 + 1 + 15 = 856 instruction cycles

If I assume 10.8us per instruction cycle
I get: 108.3 and 108.2 baud  ( close enough to 110 )


For [herb's]  machine:
---------------------------

delayCount equ 0F3h
  DelayBaudRate:
0359 20 F3  fim r0r1,delayCount  ; 2 cycles

  DBRLoop1: 
035b 71 5B  isz r1,DBRLoop1  ; 16-3=13 first pass 16 on loops
035d 70 5B  isz r0,DBRLoop1  ; 0Fh-0Fh=0  +1 for last incr

13 +1 = 14 loops or 28 cycles


   DelayBaudRateHalf:
035f 20 F3  fim r0r1,delayCount  ; as above. 2 cycles

  DBRLoop2: 
0361 71 61  isz r1,DBRLoop2 
0363 70 61  isz r0,DBRLoop2

28 cycles

0365 C0   bbl 0	;1 cycle

14 cycles TX overhead
2 + 28 + 2 + 28 + 1 + 14 = 75 instruction cycles

15 cycles RX overhead
2 + 28 + 2 + 28 + 1 + 15 = 76 instruction cycles

If I assume 10.8us per instruction cycle
I get: 1234.6 and 1218.3 baud  ( close enough to 1200 )

**************************************


[Redone Kyle's calculations:]

 0359 20 F3  fim r0r1,delayCount  ; 16 or 17 cycles overhead depending on TX or RX
 DBRLoop1: 
 035b 71 5B  isz r1,DBRLoop1  ;
 035d 70 5B  isz r0,DBRLoop1  ; this one once, so that makes 28 cycles + 2

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Herb Johnson
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